Referring to FIG. 1, an inverter 100 includes a pair of complementary MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) including a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) 102 and an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) 104. The drains of the PMOSFET 102 and the NMOSFET 104 are coupled together at an output node 106, and the gates of the PMOSFET 102 and the NMOSFET 104 are coupled together at an input node 108. The source of the PMOSFET 102 is coupled to Vcc 110, and the source of the NMOSFET 104 is coupled to a ground node 112. Such an inverter 100 of FIG. 1 is known to one of ordinary skill in the art of electronics.
For operation of the inverter 100 of FIG. 1, the threshold voltage across the gate to source of the PMOSFET 102 is typically symmetrical but has an opposite polarity from the threshold voltage across the gate to source of the NMOSFET 104, as known to one of ordinary skill in the art of electronics. For example, the threshold voltage across the gate to source of the PMOSFET 102 may be −0.3 Volts, while the threshold voltage across the gate to source of the NMOSFET 104 may be +0.3 Volts.
FIG. 2 shows a top view of an N-well 114 for fabricating the PMOSFET 102 therein and of a P-well 116 for fabricating the NMOSFET 104 therein. The N-well 114 and the P-well 116 are surrounded by a shallow trench isolation structure 118 comprised of a dielectric material such as silicon dioxide (SiO2) for example. For fabricating the PMOSFET 102 and the NMOSFET 104 of the inverter 100 of FIG. 1, a dummy gate structure 120 is initially formed over the N-well 114 and the P-well 116.
FIG. 3 shows a cross-sectional view across either line I—I in FIG. 2 for the PMOSFET 102 or across line II—II in FIG. 2 for the NMOSFET 104. Assume FIG. 3 shows the cross-sectional view across line II—II in FIG. 2 for the NMOSFET 104. In that case, the P-well 116 is formed on buried oxide 122 which is comprised of silicon dioxide (SiO2) formed on a semiconductor substrate 124 comprised of silicon, in SOI (silicon on insulator) technology. The P-well 116 is comprised of silicon, and the P-well 116 is surrounded by the shallow trench isolation structure 118.
Referring to FIGS. 2 and 3, the dummy gate structure 120 is formed over the P-well 116, and a dummy gate dielectric 126 is formed under the dummy gate structure 120. The dummy gate structure 120 is comprised of polysilicon, and the dummy gate dielectric 126 is comprised of silicon dioxide (SiO2). For the NMOSFET 104, drain and source extension junctions, 128 and 130 respectively, and drain and source contact junctions, 132 and 134 respectively, are formed typically from implantation of N-type dopant into the P-well 116.
Spacers 136 are formed at the sidewalls of the dummy gate structure 120 after formation of the drain and source extension junctions 128 and 130 and before formation of the drain and source contact junctions 132 and 134 for defining such drain and source regions 128, 130, 132, and 134. The drain and source extension junctions 128 and 130 are formed as shallow junctions for minimizing undesired short-channel effects, and the drain and source contact junctions 132 and 134 are formed as deeper junctions for maximizing the volume of silicide to be formed therein for minimizing resistance, as known to one of ordinary skill in the art of integrated circuit fabrication. The drain and source contact junctions 132 and 134 extend down to contact the buried oxide 122 in SOI (semiconductor on insulator) technology for eliminating junction capacitance, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 4, a drain silicide 142 is formed within the drain contact junction 132 for providing contact to the drain, a source silicide 144 is formed within the source contact junction 134 for providing contact to the source, and a gate silicide 146 is formed with the dummy gate structure 120. Referring to FIG. 5, an ILD (inter-level dielectric) layer 148 typically comprised of low-k dielectric materials is deposited, and the materials on the semiconductor substrate 124 are polished down until the dummy gate structure 120 is exposed. At this point, the cross-sectional view across line I—I in FIG. 2 for the PMOSFET 102 is substantially same as the cross-sectional view across line II—II in FIG. 2 as illustrated in FIG. 5 except that the drain and source extension and contact junctions 128, 130, 132, and 134 would be formed from implantation of P-type dopant into the N-well 114 for the PMOSFET 102.
Referring to FIGS. 2 and 6, FIG. 6 shows the cross-sectional view along line III—III of FIG. 2 including the dummy gate dielectric 126 and the dummy gate structure 120 disposed over the N-well 114 and the P-well 116 after formation of the PMOSFET 102 within the N-well 114 and the NMOSFET 104 within the P-well 116 as illustrated in FIG. 5. Referring to FIGS. 6 and 7, a photo-resist masking material 150 is patterned to remain over the portion of the dummy gate structure 120 disposed over the P-well 116, and the exposed portion of the dummy gate structure 120 and the dummy gate dielectric 126 over the N-well 114 is etched away to form a first gate opening 152.
Referring to FIGS. 7 and 8, a high-k dielectric 154 (i.e., a dielectric material having a dielectric constant higher than that of silicon dioxide (SiO2)) is formed on the N-well 114 at the bottom of the first gate opening 152, and the first gate opening 152 is then filled with a first metal 156. The high-k dielectric 154 on the N-well 114 forms the first gate dielectric and the first metal 156 forms the first metal gate structure of the PMOSFET 102 formed within the N-well 114.
Referring to FIGS. 8 and 9, the remaining portion of the dummy gate structure 120 and the dummy gate dielectric 126 over the P-well 116 is etched away to form a second gate opening 158. Referring to FIGS. 9 and 10, because the sidewalls 157 and 155, respectively, of the first metal gate structure 156 and the first high-k gate dielectric 154 are exposed, the etchant for etching away the dummy gate structure 120 and the dummy gate dielectric 126 over the P-well 116 may etch into the first metal gate structure 156 and the first high-k gate dielectric 154 as illustrated from FIG. 9 to FIG. 10. In addition, a metal oxide 160 may be formed on the exposed sidewall of the first metal gate structure 156.
Referring to FIGS. 10 and 11, a high-k dielectric 162 is deposited on the P-well 116 at the bottom of the second gate opening 158, and the second gate opening 158 is then filled with a second metal 164. The high-k dielectric 162 on the P-well forms the second gate dielectric and the second metal 164 forms the second metal gate structure of the NMOSFET 104 formed within the P-well 116. The first metal gate structure 156 and the second metal gate structure 164 form the dual work-function metal gate structure of the pair of complementary MOSFETs 102 and 104 of FIG. 1. In this manner, the first metal gate structure 156 and the second metal gate structure 164 are comprised of different types of metal such that the complementary MOSFETs 102 and 104 of FIG. 1 have different gates with different work-functions (i.e., dual work-functions) for the symmetrical but opposite threshold voltages.
Processes for forming the structures in the cross-sectional views of FIGS. 3, 4, 5, 6, 7, 8, 9, 10, and 11 in the prior art are known to one of ordinary skill in the art of integrated circuit fabrication. However, referring to FIGS. 1, 10 and 11, in the prior art, formation of the metal oxide 160 on the exposed sidewall of the first metal gate structure 156 results in undesired resistance between the gates of the PMOSFET 102 and NMOSFET 104. Furthermore, etching of the first metal gate 156 and the first gate dielectric 154 toward the N-well results in degradation or even failure of operation of the PMOSFET 102 formed over the N-well 114.
In addition, because the high-k gate dielectrics 154 and 162 are deposited in separate deposition processes in the prior art, the thicknesses of the high-k gate dielectrics 154 and 162 for the PMOSFET 102 and the NMOSFET 104 would vary with processing variations. Such variations of the thicknesses of the high-k gate dielectrics 154 and 162 is undesirable for controlling the threshold voltages of the PMOSFET 102 and the NMOSFET 104. A method is desired for fabricating the dual work-function metal gate structure of the complementary MOSFETs 102 and 104 without such disadvantages of the prior art.